(a) Field of the Invention
The present invention concerns a process of manufacturing a semiconductor device having at least one laminated PN-junction.
(b) Description of the Prior Art
Semiconductor devices such as transistors are manufactured, usually, by first forming, simultaneously, a number of semiconductor device units in an adjacent fashion relative to each other on a semiconductor wafer which is composed of, for example, PN lamination, followed by cutting the resulting wafer to sever same into respective individual chips of semiconductor devices, and thereafter sealing these semiconductor devices, respectively, for completion. Said cutting of the wafer is carried out by, for example, the use of a rotating grinding wheel or a scribing machine.
In certain kinds of semiconductor devices, for example, a mesa transistor, those portions skirtingly surrounding the transistor are removed by etching in order to decrease the cross sectional area of the base region thereof. The etching step is performed usually just before cutting such a wafer into a number of independent transistor chips. More specifically, this etching step is carried out by first masking the surfaces of both the base and emitter regions of the respective transistors formed on the semiconductor wafer with a masking material, for example, a wax having the property of resisting the corroding action of the etching solution which is employed. Whereby, those portions of the wafer which are located between the adjacently disposed respective transistors and which are not coated with the wax are etched away, thereby forming the so-called mesa configuration on each of the manufactured transistors. As a result of this etching step, the laminated PN-junction of the wafer located between the base region and the collector region of each transistor is exposed.
The exposed PN-junction which is encountered during the manufacturing process of a semiconductor device tends to provide cause for the degradation of the function of the produced transistor. More specifically, the severed respective chips of transistor are then subjected to the assembling steps including the bonding step and the sealing step to provide completed transistors. However, during the storage of these individual chips of transistor during or prior to the assembling steps referred to above, those regions containing the exposed PN-junctions could be easily damaged or otherwise they are easily contaminated by dust, moisture and the like, resulting in a degradation of the electrical properties of the completed transistors. In order to keep such damage or contamination of the regions containing the PN-junctions from taking place during the storage of the semiconductor devices in the manufacturing process, it is the usual practice to wash the chips of transistor after the completion of the bonding step, or to carry out a further etching by the use of an aqueous solution of sodium hydroxide and thereafter to coat the resulting surfaces of the transistor chips with a protective film consisting of, for example, a silicone resin. According to this type of procedure, however, it is difficult to expect protection of the exposed PN-junctions in the stage prior to the coating of the surfaces of the transistor chips with a protective film, and therefore no sufficient protective effect of these surfaces is attained. The problem of protection of the PN-junctions of semiconductor devices as discussed above also applies equally to semiconductor devices other than the mesa transistors, i.e., to mesa diodes, mesa thyristors, inversed mesa transistors and mesa FET's.